In a semiconductor device such as a non-volatile memory device having buried bit lines, an impurity may be selectively doped in upper portions of a semiconductor substrate to form buried bit lines in the substrate which are spaced uniformly from one another. A buried bit line formed directly in a semiconductor substrate may require minimal space.
FIG. 1 is a plan view of a conventional NOR device with a SONOS structure having buried bit lines. Bit lines 12 are formed in upper portions of a semiconductor substrate 10 doped with an impurity of a first conductivity type, e.g., a P-type impurity, by selectively doping the substrate with an impurity, e.g., an N-type impurity, of a second conductivity type opposite to that of the semiconductor substrate 10. Bit lines 12 may have a higher net doping concentration than substrate 10 and may be spaced uniformly from one another while extending in a first direction (e.g. the Y-axis direction indicated in FIG. 1). The bit lines 12 may have a stripe pattern. The word lines 14 may be formed at right angles to the bit lines 12. The word lines 14 may be spaced uniformly from one another and may cover portions of the semiconductor substrate 10 and the bit lines 12. The word lines 14 may be shaped as stripes and may cover channel regions 16 formed in the upper portions of the semiconductor substrate 10 and source/drain regions 18 formed in the bit lines 12. Bit line contacts 20 for external electrical connection may be formed at one end of the bit lines 12.
In some conventional semiconductor devices having buried bit lines, device isolation of the bit lines 12 is performed by PN junctions between the bit lines and the semiconductor substrate 10, which have opposite conductivity types. However, as semiconductor devices are miniaturized, punch-through (i.e. a breakdown due to overlapping junction depletion regions) may occur at the PN junction, resulting in a loss of device isolation. That is, as the distance between adjacent bit lines is reduced in an effort to make devices smaller, the effectiveness of PN junction isolation as a means to isolate adjacent devices may be reduced.
Furthermore, with the high integration of semiconductor devices, the gate channel length is decreased. This may result in several problems, such as a short channel effects, microscopic pattern formation, and restricted operating speed. In particular, various short channel effects may become a serious problem. For example, an increased electric field around the drain region may cause punch-through that penetrates to the potential barrier around a source region. Also, thermo-electrons may cause avalanche breakdown, and a vertical electric field may decrease the vertical mobility of carriers.